CMOS Digital Integrated Circuits：Analysis and Design （Third Edition）pdf电子书版本下载

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Chapter1 Introduction 1

1.1 Historical Perspective 1

1.2 Objective and Organization of the Book 5

1.3 A Circuit Design Example 8

1.4 Overview of VLSI Design Methodologies 18

1.5 VLSI Design Flow 21

1.6 Design Hierarchy 23

1.7 Concepts of Regularity,Modularity,and Locality 25

1.8 VLSI Design Styles 28

1.9 Design Quality 38

1.10 Packaging Technology 41

1.11 Computer-Aided Design Technology 43

Exercise Problems 45

Chapter2 Fabrication of MOSFETs 48

2.1 Introduction 48

2.2 Fabrication Process Flow:Basic Steps 49

2.3 The CMOS n-Well Process 59

2.4 Layout Design Rules 66

2.5 Full-Custom Mask Layout Design 66

Exercise Problems 73

Chapter3 MOS Transistor 83

3.1 The Metal Oxide Semiconductor(MOS)Structure 83

3.2 The MOS System under Extemal Bias 87

3.3 Structure and Operation of MOS Transistor(MOSFET) 90

3.4 MOSFET Current-Voltage Characteristics 100

3.5 MOSFET Scaling and Small-Geometry Effects 112

3.6 MOSFET Capacitances 126

Exercise Problems 138

Chapter4 Modeling of MOS Transistors Using SPICE 143

4.1 Introduction 143

4.2 Basic Concepts 144

4.3 The LEVEL 1 Model Equations 146

4.4 The LEVEL 2 Model Equations 150

4.5 The LEVEL 3 Model Equations 154

4.6 State-of-the-Art MOSFET Models 155

4.7 Capacitance Models 156

4.8 Comparison of the SPICE MOSFET Models 160

Appendix:Typical SPICE Model Parameters 162

Exercise Problems 165

Chapter5 MOS Inverters:Static 166

Characteristics 166

5.1 Introduction 166

5.2 Resistive-Load Inverter 174

5.3 Inverters with n-Type MOSFET Load 183

5.4 CMOS Inverter 194

Exercise Problems 211

Chapter6 MOS Inverters:Switching Characteristics and Interconnect Effects 215

6.1 Introduction 215

6.2 Delay-Time Definitions 217

6.3 Calculation of Delay Times 219

6.4 Inverter Design with Delay Constraints 227

6.5 Estimation of Interconnect Parasitics 238

6.6 Calculation of Interconnect Delay 249

6.7 Switching Power Dissipation of CMOS Inverters 257

Appendix:Super Buffer Design 264

Exercise Problems 267

Chapter7 Combinational MOS Logic Circuits 271

7.1 Introduction 271

7.2 MOS Logic Circuits with Depletion nMOS Loads 272

7.3 CMOS Logic Circuits 284

7.4 Complex Logic Circuits 291

7.5 CMOS Transmission Gates(Pass Gates) 304

Exercise Problems 314

Chapter8 Sequential MOS Logic Circuits 320

8.1 Introduction 320

8.2 Behavior of Bistable Elements 321

8.3 SR Latch Circuit 327

8.4 Clocked Latch and Flip-Flop Circuits 333

8.5 CMOS D-Latch and Edge-Triggered Flip-Flop 340

Appendix:Schmitt Trigger Circuit 347

Exercise Problems 350

Chapter9 Dynamic Logic Circuits 354

9.1 Introduction 354

9.2 Basic Principles of Pass Transistor Circuits 356

9.4 Synchronous Dynamic Circuit Techniques 368

9.5 Dynamic CMOS Circuit Techniques 373

9.6 High-Performance Dynamic CMOS Circuits 377

Exercise Problems 394

Chapter10 Semiconductor Memories 399

10.1 Introduction 399

10.2 Dynamic Random Access Memory(DRAM) 404

10.3 Static Random Access Memory(SRAM) 432

10.4 Nonvolatile Memory 445

10.5 Flash Memory 458

10.6 Ferroelectric Random Access Memory(FRAM) 466

Exercise Problems 469

Chapter11 Low-Power CMOS Logic Circuits 475

11.1 Introduction 475

11.2 Overview of Power Consumption 476

11.3 Low-Power Design Through Voltage Scaling 487

11.4 Estimation and Optimization of Switching Activity 498

11.5 Reduction of Switched Capacitance 504

Exercise Problems 506

Chapter12 BiCMOS Logic Circuits 507

12.1 Introduction 507

12.2 Bipolar Junction Transistor(BJT):Structure and Operation 510

12.3 Dynamic Behavior of BJTs 522

12.4 Basic BiCMOS Circuits:Static Behavior 529

12.5 Switching Delay in BiCMOS Logic Circuits 531

12.6 BiCMOS Applications 537

Exercise Problems 540

Chapter13 Chip Input and Output(I/O) 544

Circuits 544

13.1 Introduction 544

13.2 ESD Protection 545

13.3 Input Circuits 548

13.4 Output Circuits and L(di/dt)Noise 553

13.5 On-Chip Clock Generation and Distribution 557

13.6 Latch-Up and Its Prevention 562

Exercise Problems 569

Chapter14 Design for Manufacturability 571

14.1 Introduction 571

14.2 Process Variations 572

14.3 Basic Concepts and Definitions 574

14.4 Design of Experiments and Performance Modeling 580

14.5 Parametric Yield Estimation 588

14.6 Parametric Yield Maximization 593

14.7 Worst-Case Analysis 595

14.8 Performance Variability Minimization 601

Exercise Problems 604

Chapter15 Design for Testability 608

15.1 Introduction 608

15.2 Fault Types and Models 608

15.3 Controllability and Observability 612

15.4 Ad Hoc Testable Design Techniques 613

15.5 Scan-Based Techniques 616

15.6 Built-In Self Test(BIST)Techniques 618

Exercise Problems 622

References 623